VLSI Course

Introduction to Electronics and MOSFET Theory

Introduction to CMOS Process and Circuits

Introduction to Unix/Linux Commands + VI Editor Commands

ASIC Flow Overview: RTL → GDS

Verilog and Netlist Fundamentals

Timing and SDC Concepts + Design-Related Checks

Library Files: .lib, .lef, .db, Milkyway, TLU+, ITF, QRC Tech, GDS

Process Corner Definitions: SSG, TT, FFG, SF, FS + MMMC Design Environments

Full SDC Writing Rules: create_clock, set_input_delay / set_output_delay, set_clock_uncertainty, set_clock_latency, set_false_path / set_multicycle_path, set_clock_groups

Library Checks and Sanity Checks + Different Cell Types

Lab: Create complete SDC for a SoC block · Load tech LEF, cell LEF, floorplan LEF in Innovus · Setup MMMC views

Assignment: Build full MMMC + SDC + constraint checker script

Key Technologies: Cadence Innovus, Unix/Linux, VI Editor

Post Synthesis Checks · DFT Basics and Fault Modeling · Logic and Fault Simulation

SCAN Design · Introduction to BIST

Synthesis Optimization: uniqify, preserve, flatten · Wireload Model · Physical/Spatial Synthesis

Die vs Core Calculation · Utilization Planning (60–75%)

Macro Placement Rules: Channel-Based, Abutted, Notch Removal, Halo/Keep-Out Margins

Port Placement (Timing-Aware)

IR Drop Architecture: PG Rings, Vertical/Horizontal Metal Planning · Strap Width, Pitch, Offset · EM/Current Density Planning

Multi-Voltage Domain Floorplan + UPF Basics

Timing Concepts: Setup, Hold, Recovery, Removal, Pulse Width, Clock Gating Check

Lab: Floorplan a given SoC sub-block · Add stripes on M8/M9 · Create macro halos and blockages · Run early Voltus IR-drop analysis

Assignment: TCL script for automatic macro placement and blockage generation

Key Technologies: Synopsys Design Compiler, Cadence Innovus, Voltus

Placement Stages (Coarse, Detailed) · Controls and QoR

Congestion Analysis & Root Causes · Fixes: Blockages, Padding, Spreading

Timing Analysis During Placement · Setup/Hold issues

Scan Reorder · DRV Optimization · Buffer Tree Synthesis · HFNS

Timing-Driven Placement Internals · Repeater Insertion · Pin Density Estimation

Lab: Run placement + trial route · Congestion heatmap analysis · Fix congestion with blockages · Early timing optimization

Assignment: Python script — auto-parse congestion report and generate heatmap

Key Technologies: Cadence Innovus, Python

CTS Prerequisites · Pre-CTS Analysis · CTS Spec Preparation

Clock Trees: H-Tree, Fishbone, Hybrid · Post-CTS analysis and OOR reports

OCV modelling · Path grouping · Clock balancing · Clock latency calculations

Useful Skew · Target Skew/Latency · Max Transition/Cap · Multi-clock interactions

POCV/AOCV · CRPR · Antenna and latch-up · Routing optimization concepts

Lab: Build CTS (H-tree/fishbone) · Reduce skew and clock power · Fix hold violations post-CTS

Assignment: TCL auto-clock-buffer insertion on selected nets · Python extract insertion delay and skew from clock reports

Key Technologies: Cadence Innovus, Synopsys ICC2

Routing modes and constraints · Preferred direction · Track reservations

NDR rules · Via ladders · Route guides · Pin access issues

Double/Quad patterning DRC · 7nm/5nm spacing/width/enclosure/min-area rules

Antenna effect and latch-up

Lab: Complete routing · Fix DRC (spacing, cut, width, min-area) · Shield clock nets using NDRs · Repair shorts

Assignment: Python script to auto-generate DRC violation summary

Key Technologies: Cadence Innovus, Synopsys ICC2

Crosstalk, noise, distortion, ringing, ground bounce · Power supply noise

Static + Dynamic IR drop · Vector-based IR analysis

EM on signal lines and power rails · Self-heat rules · Reliability issues

Power domains, isolation, retention, level-shifters · Decap insertion strategy

Lab: Voltus static IR drop · EM signoff · Fix IR drop with extra stripes · Decap insertion

Assignment: Build an automated EM/IR reporting pipeline

Key Technologies: Cadence Voltus, Synopsys PrimeRail

Setup/Hold root causes · Full path analysis · Timing budgets

AOCV/POCV derates · xTalk-aware STA · Slew-driven timing · CRPR

Cell sizing · Buffer insertion · Vt swap · Aggressor analysis and fixes

PrimeTime ECO flows

Lab: Fix setup issues (cell sizing, buffer insertion, Vt swap) · Fix hold violations · xTalk analysis and fix · PrimeTime ECO

Assignment: Python STA report parser → Excel summary · TCL automatic ECO insertion (buffer or resize)

Key Technologies: Synopsys PrimeTime, Cadence Tempus

DRC categories: spacing, enclosure, min area, shorts/opens, density

LVS debug techniques · ERC (power/ground, floating nodes) · Antenna rules

Calibre rule decks · IC Validator · LEC (formal verification)

Lab: Run full-chip DRC · Fix ANT violations with jump metal · LVS extraction and debug

Assignment: Python auto-highlight DRC hotspots on GDS heatmap · TCL automated filler insertion flow

Key Technologies: Mentor Calibre, Synopsys IC Validator

Timing closure · Power signoff · DRC clean · FM clean · SI clean

PWV/HOLD/SETUP checks · SI double switch · Min pulse width

Common signoff issues: multi-driven nets, floating IOs, long nets, no-CLK attributes

Tapeout deliverables: GDS, SPEF, QRC extraction, Liberty timing checks

Lab: Full signoff run · Final ECO fixes · Tapeout checklist execution

Assignment: Python — generate complete tapeout package

Key Technologies: Synopsys PrimeTime, Mentor Calibre, Cadence Voltus

Low power methods · Power domains · Isolation · Level shifters · Retention flops

UPF writing · Power state table (PST) · Power intent verification

Lab: Implement UPF design in Innovus · Insert isolation and level-shifters correctly · Simulate retention behavior

Assignment: TCL — generate domain-wise isolation/LS check report

Key Technologies: Cadence Innovus, Synopsys ICC2

End-to-End Flow: Netlist → SDC → Floorplan → Placement → CTS → Routing → ECO → DRC/LVS → Signoff

Deliverable: Complete PD project (~100K instance block) · SDC/MMMC · CTS/timing closure files · IR/EM/DRC/LVS signoff package

Key Technologies: Cadence Innovus, Synopsys ICC2, PrimeTime, Calibre, Voltus

Python regex for log parsing · TCL procedure writing · Innovus API automation · OpenROAD scripting

Mini-projects: Timing ECO generator · Congestion heatmap tool · Clock tree visualization · PD flow auto-run pipeline · RTL → SDC generator

Final Project: Build a mini PD flow automation tool using Python + TCL that auto-runs the complete flow

Key Technologies: Python 3.x, TCL, OpenROAD, Innovus API

FSM design (Mealy and Moore) · Datapath elements · Adders, multipliers, shifters

Design capture and simulation methodology · Practical examples

Timing concepts: setup, hold, recovery, removal, pulse width, clock gating check

Lab: FSM and datapath design simulation and debug

Key Technologies: Synopsys VCS, Cadence Xcelium, DVE

Verilog syntax · operators · procedural statements · control statements

FSM coding · tasks and functions · advanced testbenches (clock/stimulus)

Lab: RTL module coding and testbench development in VCS / Xcelium

Key Technologies: Synopsys VCS, Cadence Xcelium, DVE

Verification plan · stimulus/response methodology · interfaces/modports · BFMs

Driver/monitor/scoreboard/checker · SV event ordering · clocking/program blocks

OOP concepts · constrained random · functional coverage · SVA (immediate + concurrent)

Lab: Full constrained random testbench with functional coverage model

Key Technologies: Synopsys VCS, Mentor Questasim, Cadence Xcelium, Verdi

UVM class hierarchy · factory/overrides · sequences/sequencers · virtual sequences

TLM · analysis ports/exports/FIFOs · reporting methods · phasing

Reusable verification environment design

Lab: Build full UVM agent + environment + test class hierarchy

Assignment: Reusable VIP-like verification component

Key Technologies: Synopsys VCS, Cadence Xcelium, Mentor Questasim, Verdi

Real SoC sub-block verification cycle · write RTL DUT · verification plan

Build UVM TB (agent/env/test) · constrained random sequences · coverage closure

Debug failures in Verdi · final verification report with metrics

Deliverable: Complete UVM testbench + coverage closure report + final verification report

Key Technologies: Synopsys VCS, Cadence Xcelium, Verdi, Mentor Questasim

Python basics · file I/O · regex for log parsing · argparse CLI tools

Pandas report analysis · Matplotlib visualization · batch processing · error handling

Lab: Parse an STA log file → generate structured CSV report

Key Technologies: Python 3.x, Pandas, Matplotlib, argparse

TCL syntax and data structures · proc writing and reuse

Innovus API commands · VCS/Xcelium TCL scripting · automated flow execution scripts

Lab: Build an auto-run Innovus PD flow script

Key Technologies: TCL, Cadence Innovus API, Synopsys VCS API

Perl basics for legacy EDA scripts · pattern matching/substitution

Python OOP for tool wrappers · data extraction pipelines · multi-file batch processing

Lab: Build a DRC parser that generates a violation heatmap

Key Technologies: Python 3.x, Perl, TCL

Timing ECO Generator (STA report → fix suggestions)

Congestion Heatmap Tool (Innovus report → heatmap)

Auto STA Report → Excel Dashboard

Key Technologies: Python 3.x, TCL, OpenROAD, xlsxwriter, Matplotlib, Pandas